A computer memory device includes arrays of memory cells and peripheral input and output (I/O) circuitry. In the array, the memory cells are arranged into rows and columns. All memory cells in each row are connected to a common word line. All memory cells in each column are connected to a common bit line. Data throughput is increased by accessing all the memory cells in a row simultaneously using the word line and transmitting data to and from the memory cells using the bit lines.
On the I/O side, data signals from the bit lines are detected by sense amplifiers and latched (stored) in peripheral circuitry known as a row buffer. Once the row's data are placed in the row buffer, subsequent requests to the same row can be serviced by accessing the data in the row buffer. Such an access is known as a row buffer hit, and can be serviced at the latency of the peripheral circuitry, without interacting with the memory cell array. To service an access request for another row, data must be accessed from the memory cell array. This access request, which will result in the contents of the row buffer being replaced, is known as a row buffer miss, and it will incur a longer latency and higher energy consumption than a row buffer hit.
Phase change memory (PCM) is a non-volatile random-access memory technology that may replace or be used in conjunction with dynamic random access memory. One specific implementation of PCM technology stores information by varying the electrical resistance of a material known as chalcogenide. Chalcogenide is a term that refers to the Group VI elements of the periodic table. PCM exploits a behavior of chalcogenide, where heat produced by the passage of an electric current through the chaicogenide switches this material between two states, crystalline and amorphous. The state of chalcogenide is retained in the absence of electrical power. Furthermore, chalcogenide can be manipulated to (e.g., two) additional distinct states, in effect increasing (e.g., doubling) the storage capacity of chalcogenide-based memory.